400G Post FEC BER and Jitter Tolerance Test for Physical Layer Chip and Module

High-speed and large-capacity transmission standards using PAM4 signaling, such as 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality. Consequently, jitter tolerance tests for SERDES, DSP, and CDR used by transceivers are required at both pre-FEC evaluations of bit error rate performance as well as at correctable/uncorrectable FEC symbol error performance.

Join this webinar to learn the following:

  • Latest 400G/800G Market trends
  • Challenges of high speed PAM4 transmission
  • Outline of FEC (Forward Error Correction)
  • Anritsu MP1900A physical layer test solutions with the FEC Analysis
  • Jitter Tolerance test based on FEC uncorrectable error criteria



Hiroshi Goto, Senior Wireline Product Specialist

Hiroshi Goto has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager. Mr. Goto holds a Bachelor’s degree in Physics from Aoyama Gakuin University. He has authored numerous industry application notes and white papers and frequently speaks on the topic of signal integrity.