See you at DesignCon 2020!

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Anritsu’s Hiroshi Goto to participate in Panel—The Case of the Closing Eyes: PAM is the Answer, or Not?

Tuesday, January 28, 4:45 PM – 6:00 PM, Ballroom F - Add to Calendar

Join this panel of experts for a lively discussion on the state of testing practices for high-speed networking technologies. This year's panel will be evaluating the pros and cons of characterization efforts for 400GbE over PAM4. Chip experts will discuss design verification challenges while the test & measurement industry veterans will provide direction on testing implementation plans. Come prepared to engage in the discussion!

See Anritsu’s latest signal integrity products at Booth 837

Anritsu will showcase its leading test solutions and techniques to verify high-speed communications featuring the latest technologies, including PCI Express® (PCIe®) 3.0/4.0/5.0 and Ethernet PAM4, during DesignCon 2020 in booth #837. Test solution demonstrations will include:

  • 400G Optical PAM4 TDECQ Test
  • 400G JTOL Test for PAM4 with FEC
  • PCIe G4/G5 LEQ RX Compliance Test
  • Automated High Speed Serial Bus RX Test
  • De-embedding with Universal Fixture Extraction
  • 110 GHz Signal Integrity Measurement

Attend our technical sessions and register for a chance to win an Echo Show & Ring!

Thursday, January 30, Great America – Room 2 - Add to Calendar

To review a description of each Technical Session click into the session boxes below.

With the advancements in electro-optical communication systems to meet the ever-increasing demands for higher data speeds, coupled with the market moving toward lowering the effective cost per bit per mile, component designers are struggling to keep costs low and still maintain better designs. Optical component analyzers play a significant role in the testing and debugging of the key components utilized in these systems.

The characterization of opto-electronic (O/E) and electro-optical (E/O) components for photonic high-speed data transmission is critical as these components not only form the building block of the communication systems, but also define the future of high-speed data in various domains of communication. Measuring the responsivity of components (such as PIN diodes, APDs, electro-absorption modulators, and modulated lasers) is crucial in today’s world. On-wafer, electro-optical ROSA/TOSA device characterization will also be very crucial for the next-generation networks to work seamlessly.

PCI Express® testing can be a daunting prospect; physical-layer testing requires tools with sophisticated protocol-aware capabilities at transfer rates of 8, 16, and up to 32 Gb/T. Anritsu and Teledyne LeCroy provide compliance test coverage with industry-leading signal generation, physical- and protocol-layer analysis and Bit Error Ratio (BER) measurement technology.

This session will equip engineers with an understanding of the test specifications, detailed test procedures, and optimal test equipment configurations to ensure their products pass PCI Express® G3/G4 TX/RX compliance testing and also introduce PCI G5 test solution.

PCIe® 5.0 has a lot in common with PCIe® 4.0, at least on paper, but making 32 GT/s function with NRZ signaling is a huge challenge. With up to 36 dB of loss finely tuned equalization—FFE at the transmitter coordinated with CTLE and DFE at the receiver—is necessary to open eye diagrams as much as 10 mV. Link training coordinates the transmitter and receiver to optimize and adapt system equalization. SerDes have to operate in loopback mode and communicate at the PHY Logical Sub-block Layer under the worst-case conditions.

In transmitter tests, the BERT error detector requests changes to the FFE taps and in receiver tests the BERT pattern generator responds to requests by altering its FFE scheme. The compliance test procedure is logged so that, should a SerDes fail a compliance test, actionable information is provided for hardware debug. This sessions discusses how PCIe meets the challenge of 32G NRZ with descriptions of the technology complemented with detailed guidance through the crucial SerDes tests.
In this session Anritsu will present the latest test techniques and requirements of the PAM4 400GbE standards. Learn how to evaluate PAM4 receivers such as SerDes with Anritsu multi-channel 100Gbps PAM4 BERT. The session will focus on 100G PAM4 signal integrity, jitter tolerance test, ISI injection/emulation, and error distribution analysis to determine that the error(s) can be corrected by FEC (Forward Error Correction).

As a follow-up to the session “400G BER and Jitter Tolerance Test for 106G (53Gbaud) PAM4 with FEC” Anritsu will conduct a live demo of 106G (53Gbaud) PAM4 BER and Jitter tolerance test. You will see the following live demonstrations:

  • 100Gbps signal integrity and various implement injection   ​

  • Inter Symbol Interference (ISI) injection and emulation​

  • 100Gbps per channel (53Gbaud PAM4) BER and Jitter Tolerance test with embedded clock recovery​

  • PAM4 Error diagnostic and error distribution analysis for FEC  

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