Get Presentation Materials from Anritsu's Speakers at DesignCon

Anritsu’s experts conducted a series of educational presentations and live demos focusing on emerging and next-generation high speed technologies and associated testing requirements at this year's DesignCon. Anritsu continues to be at the forefront of high-speed designs, offering a portfolio of test solutions used by engineers to verify leading-edge components, devices, and systems.

USB Type-C^® Standard PHY Testing
Presenter: Mike Engbretson, Teledyne LeCroy
Over the last few years, USB and DisplayPort have adopted Intel’s Thunderbolt PHY specification as a ‘building block’ for USB4^™ and DisplayPort^™ specifications at the physical layer. The highest data rates over the USB-C^® are now 20Gb/s on each lane for data throughput of 40Gb/s on two lanes for USB4 and 80Gb/s over four lanes for DisplayPort 2.0. This session will discuss the latest PHY Transmitter (Source) and Receiver (Sink) test methods for USB4 and DisplayPort 2.x as well as touch on the latest PHY logical layer (PHY-Logic) debug tools for USB Type-C system integration.

PCIe^® 5.0 Live Demo
Presenter: John James, Anritsu

• PCIe 5.0 Reciever LEQ Compliance Test
• RX LEQ and Jitter Tolerance Test
• TX LEQ Response Time Test

Time Domain Reflectometer Application for VNAs
Presenter: Michael Yang, Anritsu
The time domain reflectometer measurement has always used a signal generator to transmit an incident signal to a conductor and a scope to measure the reflection in time. With advanced development in material technology it is very expensive to use a signal generator to transmit a fast-rising incident signal and a scope to measure it. However, the vector network analyzer allows for a cost-effective solution to replace a signal generator and a scope when a fast-rising incident signal is required.

In this session we will focus on using a vector network analyzer with the time domain reflectometer measurement to achieve the measurement needed when a fast-rising signal incident occurs. There are a few advanced topics that are useful when measuring the time domain reflectometer using a vector network analyzers. The topics are:

• Advantages and disadvantages using a vector network analyzers for measuring time domain reflectometer
• Time domain fundamental: low pass time domain and bandpass time domain in vector network analyzers
• Resolution vs. bandwidth in different window types
• Examples of side lobes relating to ringing in impulse and step responses
• Using a vector network analyzer time domain to estimate effective permittivity
• Applications of time domain gating functions in vector network analyzers
• How do gating functions affect frequency responses?

Live Demo of PAM4 BER & JTOL, FEC & Burst Error Analysis
Presenter: Robert Luo, Anritsu
Please join this live demonstration of PAM4 JTOL test and FEC burst error analysis using Anritsu’s BERT Signal Quality Analyzer-R MP1900A. The demo will show:

• PAM4 BERT Product Overview & Capabilities
• PAM4 BER & Jitter Tolerance Test
• FEC Burst Error Capture & Analysis

PCIe 6.0 & Beyond: PAM4 Burst BER & Jitter Tolerance Test with FEC Uncorrectable Error Analysis
Presenter: Hiroshi Goto, Anritsu
High-speed and large-capacity transmission standards using PAM4 signaling, such as PCIe G6 and 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality. The session will focus on PAM4 BER and jitter tolerance tests for SERDES, DSP, and CDR used by transceivers where the pre-FEC evaluation of bit error rate performance is required as well as correctable/uncorrectable FEC symbol error performance.